JB-5552 – Hardware & Electronics
A leading international company in Haifa is seeking for a brilliant RTL / ASIC Designer. This position involves in-depth understanding of ASIC design flow from algorithm, RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques.
3+ years experience with ASIC/FPGA RTL design (VHDL and/or Verilog) – must. Experience with Matlab-based Verilog co-simulation and verification – must. B.sc Electrical Engineering – must. Strong knowledge of Verilog, Synthesis and Static Timing Analysis – advantage. Experience in communication theory is an advantage. Experience in Matlab programing is an advantage. Knowledge in ASIC design and architectures – advantage. MSc in Electrical Engineering an advantage.
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